From 9adacf6e8fdd4daa057ba7ee3e39f18b78041954 Mon Sep 17 00:00:00 2001
From: Alex Williamson <alex.williamson@hp.com>
Date: Fri, 28 Mar 2008 15:25:14 -0600
Subject: [PATCH] [IA64] Cleanup: TLB translation

Add a new static inline function for readability.

Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>
---
 xen/arch/ia64/vmx/vmmu.c      | 11 ++++-------
 xen/arch/ia64/vmx/vmx_fault.c |  3 +--
 xen/include/asm-ia64/vmmu.h   |  5 +++++
 3 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/xen/arch/ia64/vmx/vmmu.c b/xen/arch/ia64/vmx/vmmu.c
index 8003fd094f..851fd5bded 100644
--- a/xen/arch/ia64/vmx/vmmu.c
+++ b/xen/arch/ia64/vmx/vmmu.c
@@ -167,7 +167,7 @@ fetch_code(VCPU *vcpu, u64 gip, IA64_BUNDLE *pbundle)
 //        if( tlb == NULL )
 //             tlb = vtlb_lookup(vcpu, gip, DSIDE_TLB );
         if (tlb)
-            gpip = (tlb->ppn >>(tlb->ps-12)<<tlb->ps) | ( gip & (PSIZE(tlb->ps)-1) );
+            gpip = thash_translate(tlb, gip);
     }
     if( gpip){
         mfn = gmfn_to_mfn(vcpu->domain, gpip >>PAGE_SHIFT);
@@ -180,8 +180,7 @@ fetch_code(VCPU *vcpu, u64 gip, IA64_BUNDLE *pbundle)
             ia64_ptcl(gip, ARCH_PAGE_SHIFT << 2);
             return IA64_RETRY;
         }
-        maddr = (tlb->ppn >> (tlb->ps - 12) << tlb->ps) |
-                (gip & (PSIZE(tlb->ps) - 1));
+        maddr = thash_translate(tlb, gip);
         mfn = maddr >> PAGE_SHIFT;
     }
 
@@ -536,8 +535,7 @@ IA64FAULT vmx_vcpu_tpa(VCPU *vcpu, u64 vadr, u64 *padr)
             dnat_page_consumption(vcpu, vadr);
             return IA64_FAULT;
         } else {
-            *padr = ((data->ppn >> (data->ps - 12)) << data->ps) |
-                    (vadr & (PSIZE(data->ps) - 1));
+            *padr = thash_translate(data, vadr);
             return IA64_NO_FAULT;
         }
     }
@@ -554,8 +552,7 @@ IA64FAULT vmx_vcpu_tpa(VCPU *vcpu, u64 vadr, u64 *padr)
             dnat_page_consumption(vcpu, vadr);
             return IA64_FAULT;
         } else {
-            madr = (data->ppn >> (data->ps - 12) << data->ps) |
-                   (vadr & (PSIZE(data->ps) - 1));
+            madr = thash_translate(data, vadr);
             *padr = __mpa_to_gpa(madr);
             return IA64_NO_FAULT;
         }
diff --git a/xen/arch/ia64/vmx/vmx_fault.c b/xen/arch/ia64/vmx/vmx_fault.c
index efd874926e..cbfea2a614 100644
--- a/xen/arch/ia64/vmx/vmx_fault.c
+++ b/xen/arch/ia64/vmx/vmx_fault.c
@@ -402,8 +402,7 @@ try_again:
                 if ((data->ma == VA_MATTR_UC) || (data->ma == VA_MATTR_UCE))
                     return vmx_handle_lds(regs);
             }
-            gppa = (vadr & ((1UL << data->ps) - 1)) +
-                   (data->ppn >> (data->ps - 12) << data->ps);
+            gppa = thash_translate(data, vadr);
             pte = lookup_domain_mpa(v->domain, gppa, NULL);
             if (pte & GPFN_IO_MASK) {
                 if (misr.sp)
diff --git a/xen/include/asm-ia64/vmmu.h b/xen/include/asm-ia64/vmmu.h
index 942c2d6f79..ff26ad4eb4 100644
--- a/xen/include/asm-ia64/vmmu.h
+++ b/xen/include/asm-ia64/vmmu.h
@@ -118,6 +118,11 @@ typedef struct thash_data {
 #define INVALID_TR(hdata)      (!(hdata)->p)
 #define INVALID_ENTRY(hcb, hdata)       INVALID_VHPT(hdata)
 
+static inline u64 thash_translate(thash_data_t *hdata, u64 vadr)
+{
+    int ps = hdata->ps;
+    return (hdata->ppn >> (ps - 12) << ps) | (vadr & ((1UL << ps) - 1));
+}
 
 typedef struct thash_cb {
     /* THASH base information */
-- 
2.30.2